bumped the number of registers available on AMD64 by 4.

scheme/ikarus.compiler.altcogen.ss

@@ -325,7 +325,15 @@
 (define return-value-register '%eax)
 (define cp-register '%edi)
 (define all-registers 
-  '(%eax %edi %ebx %edx %ecx))
+  (case wordsize
+    [(4) '(%eax %edi %ebx %edx %ecx)]
+    [else '(%eax %edi %ebx %edx %ecx %r8 %r9 %r10 %r11)]))
+
+(define non-8bit-registers 
+  (case wordsize
+    [(4) '(%edi)]
+    [else '(%edi %r8 %r9 %r10 %r11)]))
+
 (define argc-register '%eax)
 
 ;;; apr = %ebp
@@ -340,10 +348,6 @@
      => cadr]
     [else (error 'register-index "not a register" x)]))
 
-
-(define non-8bit-registers 
-  '(%edi))
-
 (define (impose-calling-convention/evaluation-order x)
   (define who 'impose-calling-convention/evaluation-order)
   ;;;

scheme/ikarus.intel-assembler.ss

@@ -449,12 +449,10 @@
             (lambda (a0 a1)
               (cond
                 [(and (imm? a0) (reg32? a1))
-                 (error 'REC+RM "not here 1")
                  (if (reg-requires-REX? a1) 
                      (REX.R #b101 ac)
                      (REX.R #b100 ac))]
                 [(and (imm? a1) (reg32? a0))
-                 (error 'REC+RM "not here 2")
                  (if (reg-requires-REX? a0)
                      (REX.R #b101 ac)
                      (REX.R #b100 ac))]

scheme/last-revision

@@ -1 +1 @@
-1561
+1562